1. Field of the Invention
The present invention generally relates to read only memory (ROM) devices and more particularly to an improved ROM device that includes complementary transistors which are programmed during manufacture by selective connection of the transistors to ground.
2. Description of the Related Art
Read only memory (ROM) array chips are well known in the art. The chips generally have a ROM array core, that includes a multiplicity of ROM cells, and a periphery formed of control elements controlling the operation of the array core. The ROM array stores programs and/or data in the form of bits, where a bit is either off (a logical value of 1) or on (a logical value of 0). Each bit is stored in a single cell, which is conventionally a single gate, n-channel transistor or ROM cell. A logical 1 is implemented with a transistor which has been shut off, such that it will not conduct when voltage is applied to it and a logical 0 is implemented with an active transistor which conducts when voltage is applied to it.
Further, conventional ROM cells utilize a reference bitline, that has a voltage between the precharge voltage (Vdd) and ground level, to decrease the size of the ROM array and to increase speed. If the ROM cell has a voltage above the reference voltage, it will represent a logical value of 1. If the ROM cell has a voltage below the reference voltage, it will represent a logical value of 0. However, the voltage difference between the high/low voltage and the reference voltage is narrow, which makes it difficult to identify the difference between a logical 1 and a logical 0. Further, each of these three bitline values (high, low, and reference) has a level of uncertainty based on bitline capacitance and bitlinexe2x80x94bitline coupling. This uncertainty further reduces signal margin.
In order to save wiring levels, some conventional ROMs program the personality on the bitline side of the transistor. By doing this such designs can form the ROM utilizing only two metal levels. However, programming in this fashion causes the bitline capacitance to vary greatly depending on the ROM""s personality. In the prior ROM design, the levels of uncertainty for signal margin were great enough that many xe2x80x9cquieting groundsxe2x80x9d had to be interspersed among the bitline to reduce bitlinexe2x80x94bitline coupling. Such quieting grounds increase the size and decrease the speed of the array.
Therefore, there is a need for an improved ROM cell that avoids the disadvantages associated with single transistor ROM cells and which provides increased performance without substantially increasing the size or decreasing the speed of the ROM array.
The invention described below provides such a structure.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional ROM devices the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved ROM device that includes complementary transistors which are programmed during manufacture by selective connection of the transistors to ground.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, a read only memory (ROM) cell array that has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.
The first transistor and the second transistor include gates connected to or part of a wordline. The second transistor comprises a complement transistor of the first transistor. The ROM cell shares the first drain and the second drain with corresponding drains of an adjacent ROM cells in the array.
The invention also includes a method of forming a read only memory (ROM) cell that includes forming a first drain of a first transistor such that the first drain is connected to a true bitline, forming a second drain of a second transistor such that the second drain is connected to a complement bitline, and forming a first source of the first transistor and a second source of the second transistor such that either the first source or the second source is connected to ground. The connection of the first source or the second source to the ground programs the ROM cell.
The forming of the first source and the second source only connects either the first source or the second source to the ground and insulates the other of source from electrical connections.